1. Field of the Invention
The present invention relates to a semiconductor device, and particularly relates to a semiconductor device using an internal operation voltage used in each block constituting the semiconductor device. The present invention also relates to a data processing system using the semiconductor device.
2. Description of Related Art
In recent years, an internal operation voltage of a semiconductor device has been reduced along with downscaling of a semiconductor process. For example, in a conventional DRAM (Dynamic Random Access Memory) described with reference to FIG. 3 of Japanese Patent Application Laid-open No. 2002-56671, an internal operation voltage VPERI that is lower than an external voltage VDD is used. A signal output from the semiconductor device to an external device is level-shifted from the internal operation voltage VPERI to the external voltage VDD before being output.
To explain an operation voltage of a DRAM, for example, a DDR2 SDRAM of 60-nm generation has an external voltage VDD of 1.8 V, a peripheral circuit voltage VPERI of 1.3 V, and an array-system circuit voltage VARY of 1.2 V. Meanwhile, a DDR3 SDRAM of 50-nm generation has reduced voltages of the external voltage VDD of 1.5 V, the peripheral circuit voltage VPERI of 1.0 V, and the array-system circuit voltage VARY of 1.0 V. In the 50-nm generation, the peripheral circuit voltage VPERI is equal to the array-system circuit voltage VARY, because a trend toward a decrease of the peripheral circuit voltage VPERI is different from that of the array-system circuit voltage VARY. That is, the array-system circuit voltage VARY cannot be easily reduced any more, considering physical constants of memory cells, such as a memory cell capacitance, a Vth offset of a sense amplifier, and a bit line capacitance, and thus the array-system circuit voltage VARY cannot be reduced along with a reduction trend of a processing dimension.
However, when the peripheral circuit voltage VPERI becomes low to have a very small difference between the peripheral circuit voltage VPERI and the array-system circuit voltage VARY as described above, an ON-resistance of a column switch becomes relatively high and movement of an electric charge via the column switch becomes slow. Therefore, it becomes difficult to write data from an IO line pair to a bit line pair and read data from a bit line pair to an IO line pair.
As for a row-system signal, a word line is started by using a voltage VPP that is higher than the external voltage VDD. However, when the internal operation voltage VPERI becomes lower, the difference between the internal operation voltage VPERI and the voltage VPP becomes larger. Therefore, a level conversion from VPERI to VPP takes time, and thus start of a word line becomes slow.